Credit: Ultrasoc

UltraSoc hosts Bristol RISC-V meetup as it looks to expand

Sharing the latest details on a new open source processor technology
7th November 2018

UltraSoc has hosted its first UK meetup around the RISC-V processor technology in Bristol.

“This is the first time that we have hosted a specific RISC-V event to a local, UK, audience and we were not sure how it would be received,” said Jo Windel, UltraSoC Marketing Manager. “We needn’t have worried… The event was very well attended and it was interesting to see quite a mixed audience, from students interested in getting involved in projects related to RISC-V, engineers and designers, through to partners and even potential customers. Many of the attendees were meeting for the first time and benefited from hearing about different projects and experiences of using the RISC-V architecture, which is great.”

UltraSoc has a design centre here in Bristol, developing technology that sits in chips to monitor what’s happening. This has been used so far to debug all kinds of complex system-on-chip (SoC) devices (hence the name), but it recently launched the second generation of its software tools that will allow the chips to be monitored while out in the field.

“The core idea is we put IP into chips that helps get information out that allows you to optimise software for safety and security,” said Rupert Baines, chief executive.

“The fundamental is the embedded silicon IP and that’s where most of our focus has been but the corollary to that is what do you do with the information. The monitors we have are very smart and configurable so you need a way to get information in to configure them.”

This opens up a huge market in data centres and safety-critical applications that need close monitoring, and the company is planning to expand as a result.

“We have 30 people now with six in Bristol, and we’re going to building sales presence globally, but engineering will continue to be Cambridge and Bristol,” he said.

“It’s hard to find good people, recruiting is difficult. It’s not constraining us but it’s a good thing for engineers,” he added.

RISC-V, an open source processor similar to the MIPS processor, is just one of the technologies that UltraSoC supports.

“We have seen momentum really picking up over recent months throughout other parts of the world, especially in the USA, but we felt the UK is seriously lagging in terms of engaging with RISC-V,” said Windel.

Gajinder was joined by Simon Davidmann of Imperas, who worked with UltraSoc on that development tool and outlined his company’s own developments in the RISC-V sphere. Dave McEwan from the University of Bristol also shared his views from an academic perspective.

“We think this first UK RISC-V Meetup went so well, we are going to do it again [in Cambridge], and there will also be a second Meetup in Bristol in the coming months,” said Windel.

Join the Bristol RISC-V Meetup Group at Bristol.